| 摘要 |
PROBLEM TO BE SOLVED: To reduce jitter and wander of an output signal of a clock phase synchronizing circuit without speeding a circuit operation up. SOLUTION: A pseudo-synchronization latch signal 502 with fixed phase relation with an output phase comparison signal 601 of a phase comparison circuit 6 is outputted by utilizing a sampling clock 501 with offset provided with frequency offset of frequency deviation of an input signal 200 or more at N-times (N is an integer >=2) of phase comparison frequency and a comparison clock 301 by a pseudo-synchronization control signal generation circuit 5. Output of a voltage control oscillator 4 is controlled by detecting subtle fluctuation of a phase from a sampling clock cycle by a phase difference sampling circuit 8 and generating digital phase control information without an error by the pseudo-synchronization latch signal 502 at a phase control information latch circuit 10. |
