| 摘要 |
A systolic video encoding system processes image data from a frame buffer at a core clock rate that is independent of the sample rate of the image data. The video encoder of this invention uses the core clock rate of the host image processing system to process image from the frame buffer at this core clock rate. The image data is pumped out of the frame buffer, processed by each of the processes of the video encoder when the data reaches each of the processes, and the encoded samples are stored in a raster sample buffer for subsequent processing. The image data is continually pumped out of the frame buffer at the core clock rate until the raster sample buffer is full. As the samples are extracted from the raster sample buffer, subsequent image data is pumped into the video encoding system, producing a systolic processing effect. By allowing operation at a core clock rate that is independent of, and substantially higher than, the image sample rate, elements of the system can be used in a time-shared manner, thereby reducing the cost and size of the video encoding system.
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