Redundant multiplexer for semiconducting memory arrangement improved to minimise the transition time to a redundant bit line in the event of a bit line fault - shifts bit lines with control or switching signal by number of faulty bit lines so redundant bit lines take the place of bit lines nearest to central bus

摘要

The multiplexer has information stored as to which bit line is to be replaced and generates a control or switching signal in a decoder for selection of two redundant areas with the redundant bit line on both sides of a central bus. When one or more faulty bit lines (X) are detected, all following bit lines are shifted by the control or switching signal by the corresp. number of faulty bit lines so that the redundant bit lines (A,B) take the place of the bit lines nearest to the central bus.