| 摘要 |
PURPOSE: A column address control device is provided to minimize a clock timing skew of a column address by increasing the number of a Y decoder depending on increase of the chip size by using a plurality of column address counters. CONSTITUTION: The column address control device includes a plurality of memory cell arrays(10¯17) consisting of a plurality of memory cells. A buffer(20) buffers an address(ADD). A control unit(100) receives a command(CMD) to produce a column control signal(COLC). Column address counters(110,120) count the address(ADD) inputted via the buffer(20) depending on the column control signal(COLC) in order to produce a column address(CADi). A plurality of Y decoders(50-53) receive the column address(CADi) from the column address counters(110,120) to enable a corresponding column of the plurality of columns within the memory cell arrays(10¯17).
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