发明名称 |
Power efficient line driver |
摘要 |
A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.
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申请公布号 |
US6281747(B2) |
申请公布日期 |
2001.08.28 |
申请号 |
US20010769234 |
申请日期 |
2001.01.24 |
申请人 |
TRIPATH TECHNOLOGY, INC. |
发明人 |
AHUJA BHUPENDRA K.;DELANO CARY L.;TRIPATHI ADYA S. |
分类号 |
H03F1/34;H03F1/02;H03H11/12;H04L25/02;(IPC1-7):H03F1/36;H03F3/04 |
主分类号 |
H03F1/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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