| 摘要 |
Provided is a semiconductor device having an I/O buffer cell capable of performing a timing verification test of high accuracy. A phase comparator (2) compares the phase of data (DATA) and that of a clock (CLK) and outputs a phase comparison result to a first input of an MUX (3). A test mode signal (STM1) inputted from a test mode terminal (14) is provided to the control input of the MUX (3) through a test mode input section (4). The MUX (3) receives at its second input the output signal of an internal logic (50) through a signal input section (9) and, based on the test mode signal (STM1), outputs either the phase comparison result or the output signal of the internal logic (50), to the input section of a driver (8).
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