发明名称 METHOD FOR FORMING MULTILAYER INTERCONNECTION STRUCTURE AND MULTILAYER INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for forming a fine pattern multilayer interconnection structure having low contact resistance and parasitic capacitance. SOLUTION: The method for forming a multilayer interconnection structure comprises a step for forming an SiN film 88, a first insulation film 90, an etching stop layer 92, and a second insulation film 94 on a lower layer interconnection 16, a step for opening contact holes 98 to expose the SiN film, step for filling the contact holes while forming a protective film 100 on the second insulation film, a step for forming an etching mask 102 on the protective film, a step for etching the protective film under etching conditions that the etching rate of the protective film is higher than that of the second insulation film to expose the second insulation film and keeping the upper surface of the protective film higher than the etching stop layer in the contact hole, a step for etching the insulation film under etching conditions that the etching rate of the protective film is lower than that of the second insulation film to make interconnection trenches and leaving the protective film in the contact hole not to expose the lower layer interconnection, a step for re moving the etching mask and the protective film including that in the contact holes, and a step for filling the contact holes and the interconnection trenches with metal.
申请公布号 JP2001230317(A) 申请公布日期 2001.08.24
申请号 JP20000036149 申请日期 2000.02.15
申请人 NEC CORP 发明人 MATSUMOTO AKIRA
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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