| 摘要 |
PROBLEM TO BE SOLVED: To provide an inexpensive decoder of satisfactory data quality, capable of reducing memory capacity, while preventing the deterioration of data quality. SOLUTION: Concerning the data of 24 bits successively inversely quantized by an inverse quantizing circuit 12, a maximum shift amount to shift data to the side of MSB, without omitting effective bits, is detected by a shift amount detecting circuit 21, and the minimum shift amount of data in the same block is detected by a shift control circuit 22. Thus, a first shift circuit 24 performs shifting and high-order 16 bits are stored in a memory circuit 25 for data. After the data for all blocks are stored in the memory circuit 25 for data, the data are read out successively, the shift amount is controlled to the bottom value of blocks and the data are re-stored in the memory circuit 25 for data. Then, these data are read out, decoded by a converting circuit 14 and outputted after the value is controlled by a second shift circuit 15. 16 bits are sufficient for the memory circuit 25 for data.
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