| 摘要 |
PROBLEM TO BE SOLVED: To provide a means by which high speed data access to a memory array can be performed. SOLUTION: This device is a hybrid decoder/scan register data I/O 300 system based on a group of scan registers 304 (1),..., 304 (s) connected to a train of memory arrays 600 (bit line 602) and providing high speed data access to a selected point. A device interfacing to the memory arrays is a long register 302 constituted of a series of scan register blocks 304. Data inputted/outputted to/from the memory arrays is transmitted by a parallel system. A data I/O for a specific memory address or a memory data block is sent to one input port (or output port) out of scan register blocks 304 from a serial data I/O through a group of switches 314 controlled by decoder circuits 316, 320. This hybrid data I/O circuit provides high speed access to a selected point in a column circuit of a memory arrays while keeping an efficient and high speed serial output provided by a scan chain data register. |
