摘要 |
<p>PROBLEM TO BE SOLVED: To reduce man-hours required for designing a dedicated clock signal generating circuit for generating a clock signal which is required for designing communications equipment. SOLUTION: In a source clock signal S102 generated by a clock signal generating circuit 102, an edge is detected by an edge detecting circuit 103 and the number of edges is counted by a counter 104. When a count value becomes a preset count value S101, the counter 104 is reset and repeats count operation. When the count value becomes the set count value, the source clock signal S102 is masked by a clock signal change circuit 105, so that a baud rate control clock signal S105 can be generated. Input data S106 are latched by the output baud rate control clock signal S105, every time the clock signals of a prescribed number rise, and are outputted as an output signal S107.</p> |