发明名称 CLOCK SIGNAL GENERATOR AND COMMUNICATIONS EQUIPMENT USING THE SAME
摘要 <p>PROBLEM TO BE SOLVED: To reduce man-hours required for designing a dedicated clock signal generating circuit for generating a clock signal which is required for designing communications equipment. SOLUTION: In a source clock signal S102 generated by a clock signal generating circuit 102, an edge is detected by an edge detecting circuit 103 and the number of edges is counted by a counter 104. When a count value becomes a preset count value S101, the counter 104 is reset and repeats count operation. When the count value becomes the set count value, the source clock signal S102 is masked by a clock signal change circuit 105, so that a baud rate control clock signal S105 can be generated. Input data S106 are latched by the output baud rate control clock signal S105, every time the clock signals of a prescribed number rise, and are outputted as an output signal S107.</p>
申请公布号 JP2001230660(A) 申请公布日期 2001.08.24
申请号 JP20000039510 申请日期 2000.02.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHIO TAKATOSHI;TAHIRA YOSHIHIRO;STEFAN KAU;KIEFNER MARCUS
分类号 G06F1/06;H03K5/00;H03K5/156;H03K17/00;H04L7/02;H04L7/033;(IPC1-7):H03K5/00 主分类号 G06F1/06
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