| 摘要 |
A data storage apparatus includes a latch having first and second storage nodes, a first pass transistor coupled to the first storage node, a row line coupled to a gate of the first pass transistor, and a row driver coupled to the row line. The row driver is configured to drive the row line to three different voltage levels. The three different voltage levels included a low logic level voltage, a full supply high voltage level, and a reduced high voltage level. The reduced high voltage level is greater than the low logic level voltage and less than the full supply high voltage level. A method of manipulating a memory cell having a latch having a first storage node with first and second series connected pass transistors coupled to the first storage node and a bit line coupled to the second pass transistor, includes driving the bit line to a low logic level voltage; applying a full supply high voltage level to a gate of the first pass transistor and to a gate of the second pass transistor; applying the low logic level voltage to the gate of the first pass transistor and to the gate of the second pass transistor; precharging the bit line to a high level; and applying a reduced high voltage level to the gate of the first pass transistor and to the gate of the second pass transistor, wherein the reduced high voltage level is greater than the low logic level voltage and less than the full supply high voltage level.
|
