发明名称 Method of manufacturing a DRAM capacitor with increased electrode surface area
摘要 A method of manufacturing a capacitor of a dynamic random access memory cell is disclosed. The method includes forming a capacitor opening through a dielectric isolation interlayer to expose a buried contact area. A conductive bottom plug is subsequently formed in a bottom portion of the capacitor opening and makes an electrical connection with the contact area. A conductive spacer is formed on the sidewall of the opening and then a dielectric spacer is formed on the sidewall of the conductive spacer. Such leaves a channel in the center of the capacitor opening. A conductive center column is therefore in the channel. Subsequently, the dielectric spacer is removed while leaving the conductive sidewall spacer, center column, and bottom plug to serve as a bottom storage node of the capacitor. Finally, a capacitor dielectric layer and a top storage node are formed to complete the capacitor fabrication.
申请公布号 US6277688(B1) 申请公布日期 2001.08.21
申请号 US20000609267 申请日期 2000.06.30
申请人 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION 发明人 TSENG HORNG-HUEI
分类号 H01L21/02;H01L21/8242;(IPC1-7):H01L21/824 主分类号 H01L21/02
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