Method for making partial full-wafer pattern for charged particle beam lithography

摘要

Disclosed is a method for making a partial full-wafer pattern for charged particle beam lithography based on circuit design data. This method has the steps of: conducting the interlayer operation between the circuit design data of a pattern of lithographed layer and the circuit design data of a pattern of base layer underlying the lithographed layer to extract a product-set pattern; and making data of partial full-wafer pattern by setting the product-set pattern to be a target region of partial full-wafer pattern.