发明名称 MEMORY DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To solve the problem of a flash memory that erasure of charges from a floating gate is slower as compared with the program time of Fowler Nordheim tunnel current not using thermoelectron, and to provide a memory device in which the operating speed is increased by lowering the operational bias. SOLUTION: Transport of electrons from a floating gate 16 is accelerated during erase cycle while reducing the erase voltage by introducing silicon heterostructure thermoelectron diodes 24a, 24b including intrinsic polysilicon regions 17a, 17b and an additional barrier is provided against charge leak by the intrinsic polysilicon regions thus obtaining a memory device in which a thin tunnel oxide can be used while shortening the read/write cycle.</p>
申请公布号 JP2001223281(A) 申请公布日期 2001.08.17
申请号 JP20000368529 申请日期 2000.12.04
申请人 HITACHI LTD 发明人 NAKAZATO KAZUO
分类号 G11C16/04;H01L21/28;H01L21/8247;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 主分类号 G11C16/04
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