发明名称 Buffer circuit
摘要 An output buffer circuit of a Pseudo Emitter Coupled Logic (PECL) uses a common level which is generated by a resistance division so that the common level is unstable to follow to a gradient of power source variation and an output signal level of the output buffer circuit is apt to be off from a level of the PECL. An output buffer circuit of PECL according to the present invention comprises: a first output terminal; a second output terminal; a first resistor connected between the first output terminal and a output terminal of a common level generator; a second resister connected between the second output terminal and the output terminal of the common level generator; and a driver circuit which makes a current from the first output terminal to the second output terminal through the first resistor and second resistor when a first input signal and a second input signal complementary to the first input signal result a first data, and makes a current from the second output terminal to the first output terminal through the second resistor and the first resistor when the first input signal and the second input signal result a second data; a common level which follows its fluctuation to that of power source is supplied to the connecting point of the first and second resistors.
申请公布号 US2001013794(A1) 申请公布日期 2001.08.16
申请号 US20000728103 申请日期 2000.12.01
申请人 NEC CORPORATION 发明人 TAKEUCHI JUNICHI;NAKANO FUMIO
分类号 H03K19/086;H03F1/30;H03F3/45;H03K19/0175;H03K19/0185;H04B10/04;H04B10/06;H04B10/14;H04B10/26;H04B10/28;(IPC1-7):H03K19/094 主分类号 H03K19/086
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