发明名称 |
Semiconductor memory device having a multi-layer interconnection structure suitable for merging with logic |
摘要 |
Signal lines running within a sense amplifier band provided extending in a row direction in a memory array portion are formed in a hierarchical structure having an upper interconnection layer and a lower layer interconnection layer. Thus, a semiconductor memory device suitable for merging with logic and capable of effectively utilizing a multi-layer interconnection structure in the memory array portion can be provided.
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申请公布号 |
US2001013659(A1) |
申请公布日期 |
2001.08.16 |
申请号 |
US20000748140 |
申请日期 |
2000.12.27 |
申请人 |
NODA HIDEYUKI;FUJINO TAKESHI |
发明人 |
NODA HIDEYUKI;FUJINO TAKESHI |
分类号 |
G11C11/401;G11C7/18;H01L21/8242;H01L27/02;H01L27/10;H01L27/108;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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