Multiple chip component with wireless packing has dies or chip elements with bumps on lower line frames, upper line frames coupled to dies, connecting rails interconnected in pairs

摘要

The component has lower line frames (11), dies or chip elements with bumps on lower line frames with source and gate solder bump arrays, upper line frames (13), each coupled to a die with bumps and containing lines and four rails interconnected in pairs with sides connected to the frames. Each lower frame has lines with drain connections coupled to dies with bumps. Each upper frame has lines coupled to gate and source connections on a die. Independent claims are also included for the following: a method of manufacturing a chip component, especially an improved method of packing several DMOS components.