| 摘要 |
PROBLEM TO BE SOLVED: To provide a buffer circuit capable of suitably preventing a through current even while providing a CMOS inverter circuit on the output stage. SOLUTION: This buffer circuit is provided with an inverter circuit 3, a timing control circuit 20 composed of the parallel circuit of an OR circuit 21 and an AND circuit 22 and an output stage CMOS inverter circuit 10 or the like composed of the serial circuit of a P channel MOS transistor TRp and an N channel MOS transistor TRn. The timing control circuit 20 respectively forms a gate control signal Nin of the transistor TRn for forming the ON period of the transistor TRn within the OFF period of the transistor TRp and a gate control signal Pin of the transistor TRp for forming the ON period of the transistor TRp within the OFF period of the transistor TRn so as not to simultaneously turn on the transistor TRp and the transistor TRn.
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