| 摘要 |
The present invention relates to a method and an apparatus (1158, 1171-1173, 1180-1184, 1188) for decoding blocks of data encoded using a plurality of variable-length code words. Preferably, the encoding used is Huffman coding. The blocks also comprise fixed-length, not-encoded fields and variable-length, not-encoded bit fields. The code words are interleaved with the variable-length, not-encoded bit fields. The apparatus (1158, 1171-1173, 1180-1184, 1188) includes a preprocessing logic unit for removing the fixed-length, not-encoded fields. The preprocessing logic unit outputs the variable-length code words interleaved with the variable-length, not-encoded bit fields, as well as signals indicating positions of the fixed-length, not-encoded fields in the data blocks. The apparatus (1158, 1171-1173, 1180-1184, 1188) also includes a circuit that synchronously passes the position-indicating signals to an output of the apparatus with the data being decoded. Thus, if there is a multiplicity of variable-length coded data between the fixed-length, not-encoded fields on the input of the apparatus (1158, 1171-1173, 1180-1184, 1188), a multiplicity of corresponding decoded data appears on the output of the apparatus (1158, 1171-1173, 1180-1184, 1188) between any two position-indicating signals corresponding to the fixed-length not-encoded words on the input.
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