| 摘要 |
PURPOSE: A tap controller of a JTAG(Joint Test Access Group) circuit is provided to prevent the wrong operation in testing a board by including a flip-flop for removing the glitch included in the clock signal, which is generated in a tap controller. CONSTITUTION: The tap controller of the JTAG circuit includes AND gates(AND1-AND6), flip-flops(DFF20-DFF23), inverters(I1-I4) and NAND gates(NAND6, NAND7). The flip-flops (DFF20-DFF23) output the output signal of the AND gates(AND1-AND4) and are reset by the test reset bar signal(TRST). The inverters(I1-I4) reverse each test clock(TCLK). The NAND gates(NAND6, NAND7) output the output signal of the flip-flops (DFF20, DFF22) and inverters(I1, I3) with the control signals(CLOCKIR, CLOCKDR). The AND gates(AND5, AND6) output the output signal of the flip-flops (DFF21, DFF23) and inverters(I2, I4) with the control signals(UPDATEIR, UPDATEDR).
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