| 摘要 |
PURPOSE: A data path circuit of semiconductor memory device is provided to reduce delay time by dividing a data bus line and connecting an intermediate buffer at each divided data bus line. CONSTITUTION: The first and second data bus line driving parts(110,120) operate selectively in response to an address signal, and their output terminals are connected to each other. The first data bus line precharge part(210) is connected to output terminals of the first and second data bus line driving parts(110,120). The first data bus line(310) is connected to an output terminal of the first data bus line precharge part(210). The first intermediate buffer(410) is connected to the first data bus line, and a common data bus line(700) is connected to an output terminal of the first intermediate buffer. A common data bus line precharge part(500) is connected to the common data bus line. The third and fourth data bus line driving parts(130,140) operate selectively in response to the address signal, and their output terminals are connected to each other. The second data bus line precharge part(220) is connected to output terminals of the third and fourth data bus line driving parts. The second data bus line(320) is connected to an output terminal of the second data bus line precharge part. The second intermediate buffer(420) is connected to the second data bus line. A common data bus line output signal receiving part(600) is connected to the common data bus line.
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