发明名称 Semiconductor device having a test circuit
摘要 A semiconductor memory device includes a memory circuit from which data is read in correspondence with a first reference clock signal. A multiplexer outputs the data read from the memory circuit in correspondence with the second reference clock signal. A comparison determination circuit receives the data read from the memory circuit via the multiplexer and compares the read data with an expected data value in correspondence with the second reference clock signal to generate determination result data.
申请公布号 US2001009524(A1) 申请公布日期 2001.07.26
申请号 US20010761727 申请日期 2001.01.18
申请人 FUJITSU LIMITED 发明人 KOTO TOMOHIKO
分类号 G01R31/28;G06F11/22;G06F12/16;G11C11/401;G11C11/407;G11C29/12;G11C29/38;G11C29/44;H01L21/822;H01L27/04;(IPC1-7):G11C29/00 主分类号 G01R31/28
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