Integrated circuit design exhibiting reduced capacitance

摘要

A reduced capacitance architecture for integrated circuits and particularly for memory integrated circuits is disclosed. The integrated circuit has a plurality of levels including first and second levels. A first signal conductor extends within the first level. A second signal conductor also extends within the first level and is positioned adjacent to and in close proximity with the first signal conductor. The second level is positioned adjacent to the first level and includes a third signal conductor extending within it. The third signal conductor is positioned laterally between the first and second conductors to eliminate vertical parallel plate capacitance.