| 摘要 |
A sample and hold circuit having a semiconductor with a field effect transistor therein. The field effect transistor has a channel in the semiconductor, a source region in the semiconductor, a drain region in the semiconductor a front-gate disposed over the channel, and a back-gate in the semiconductor under the channel. The front-gate and back-gate are configured to control a flow of carriers in the semiconductor through a length of the channel between the source region and the drain region. A capacitor is connected to one of the drain and source regions. The other one of the source and drain region is configured for coupling to an input signal. A switch is responsive to a sampling signal to electrically connect a constant electrical potential between one of the source and drain regions and back-gate during a tracking phase. In one embodiment, the sample and hold circuit includes a second switch to electrically a second constant potential between the front-gate and one of the source and drain. With such an arrangement, non-linearities arising from variations in both the voltage between the source/drain and back-gate (V(s/d)b) and between the source/drain and front-gate (V(s/d)g) are compensated leading to a more linear sample and hold circuit. In a second embodiment, the second switch electrically connects a fixed potential to the front-gate during the tracking phase. With such an arrangement, non-linearities arising from variations in the voltage between the source/drain and back-gate (V(s/d)b) are compensated leading to a more linear sample and hold circuit. Further, because the non-linearities due to Vsb are dealt with, the need for a large (V(s/d)g) (with the potential for voltages exceeding the supply voltage) is reduced. Hence circuit according to the invention yields reduced harmonic distortion without the need for large on-chip voltages.
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