| 摘要 |
PURPOSE: To provide a semiconductor circuit which latches the data in accordance with a plurality of clock signals with reduced capacity of signal line. CONSTITUTION: This data latch circuit includes a master flip-flop 2 and a slave flip-flop 3. The master flip-flops 2 and 44 fetch the 1st signals (d) in response to a 1st clock signal (a), hold the 1st data accordant with the signals (d) in response to a 1st clock signal (a) and outputs the 1st data as the 2nd signals (e, f). The flip-flop 3 fetches the 2nd data corresponding to the 2nd signal (e) in response to the OR of the clock signals (a) and one or plural 2nd clock signals (c), holds the 2nd data in response to the OR and then outputs a 3rd signal (g) corresponding to the 2nd data.
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