| 摘要 |
PROBLEM TO BE SOLVED: To provide a matched filter circuit having a decreased number of utilized elements in a circuit configuration and a reduced area in the layout design of an LSI in comparison with a conventional matched filter. SOLUTION: A delay circuit 121 delays an input signal X(t), four identification circuit 401-404 individually compare the signal by 16-bits each with an identification code, and adders 361-363 add the results. Since overlapping is produced in the sequence of bit arrangement in this process, FIFO 501, 502 give a delay of one bit to 1-16 bits and 49-64 bits and give a delay of 2-bits to the output of the adder 362, and the adder 363 adds the results. The delay circuit 121 can be sufficiently built of 16 bits configuration (1/4 to a conventional delay circuit). |
