| 摘要 |
An FET and DRAM using a plurality of such FETs wherein each transistor has a body region (27) of a first conductivity type including a relatively high VT region (p) and a relatively low VT region (p-), the high VT region disposed contiguous with the low VT region. A pair of source/drain regions (23, 25) of opposite conductivity type are disposed on a pair of opposing sides of the low VT region. The transistor includes a gate oxide (31) over the body region and a gate electrode (29) over the gate oxide and spaced from the body region. The body region is p-doped or n-doped with the high VT region more heavily doped than the remainder of the body. In a further embodiment, the FET includes a body region of a first conductivity type which includes a relatively low VT region and a first pair of relatively high VT regions on a first pair of opposing sides of the body. A pair of source/drain regions of opposite conductivity type are disposed on a second pair of opposing sides of each of the low VT region. A gate oxide is disposed over the body region and a gate electrode is disposed over the gate oxide and spaced from the body region.
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