| 摘要 |
<p>In one embodiment, the process comprises depositing a CVD metal oxide layer on the substrate at a substrate temperature of less than or equal to about 480 °C and annealing the metal oxide layer. In one aspect, annealing comprises providing a first substrate temperature between abut 600 °C and 900 °C, maintaining the first substrate temperature for a time period of between about 0.1 seconds and 30 minutes, providing a second substrate temperature between about 500 °C to 600 °C, and maintaining the second substrate temperature for a time period of at least 10 minutes. In another embodiment, the process comprises depositing a first electrode; depositing a CVD metal oxide layer on the first electrode at a substrate temperature of less than or equal to about 480 °C; and depositing a second electrode on the oxide layer. In one aspect the metal oxide layer is annealed prior to deposition of the second electrode. In another aspect, the metal oxide layer is anneal subsequent to deposition of the second electrode. In one aspect, annealing comprises providing a first substrate temperature between about 600 °C and 900 °C, maintaining the first substrate temperature for a time period of between about 0.1 seconds and 30 minutes, providing a second substrate temperature between about 500 °C to 600 °C, and maintaining the second substrate temperature for a time period of at least 10 minutes. In another aspect, the present invention provides a capacitor comprising a platinum bottom electrode, a platinum top electrode, and a dielectric layer disposed between in which the capacitor has a current leakage of less than 10 fA/cell.</p> |
