| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay fixing loop having a fast locking time and small jitter. SOLUTION: In a delay fixing loop for compensating skewness in a SDRAM, this circuit is provided with a delay clock generating means generating a delay clock signal by delaying an external clock signal by the skewness, a signal generating means for generating a control signal responding to the external clock signal and the delay clock signal, a first delay means generating a first delay fixing loop clock signal by delaying the external clock signal with a first delay unit responding to the control signal, a second delay means generating a second delay fixing loop clock signal by delaying the first delay fixing loop clock signal with a second delay unit responding to the control signal, the first delay unit is larger than the second delay unit. |
