| 摘要 |
A clock doubler circuit and method that accept an input clock signal and provide therefrom an output clock signal having twice the frequency of the input clock signal. One circuit according to the invention includes an input clock terminal supplying a input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 90 degrees offset from the input clock signal. The selected clock signal is then combined with the input clock signal in an output clock generator to generate an output clock signal having twice the frequency of the input clock signal. In one embodiment, the clock doubler circuit includes a delay stage comprising a delay element that can selectively add a half-unit delay to the input clock signal.
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