| 摘要 |
PURPOSE: A clock generator of a synchronous memory device is provided to generate primary internal clocks from input clocks and then control a plurality of internal clock generators using an external clock enable signal and a respective function control signal to supply the particular function clocks to respective function buffers. CONSTITUTION: In a clock generator of a synchronous memory device, a clock buffer(10) inputs an external clock to generate an internal clock. An enable buffer(20) inputs an external clock enable signal. A latch(60) inputs the output signal of the enable buffer and the output signal of the clock buffer to temporarily memorize an external clock enable signal. A plurality of function buffers(80) are synchronized and driven with the clock. A device(70) for generating a control signal controls the functions of the plurality of function buffers. Devices(30,40,50) for generating internal clocks generate main internal clocks output to the plurality of function buffers depending on the external clock enable signal output from the latch and the signal output from the device for generating a control signal.
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