发明名称 |
Thread signaling in multi-threaded network processor |
摘要 |
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described. |
申请公布号 |
AU4311601(A) |
申请公布日期 |
2001.07.09 |
申请号 |
AU20010043116 |
申请日期 |
2000.12.08 |
申请人 |
INTEL CORPORATION |
发明人 |
GILBERT WOLRICH;DONALD HOOPER;DEBRA BERNSTEIN;MATTHEW J. ADILETTA;WILLIAM WHEELER |
分类号 |
G06F9/38;G06F9/48 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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