| 摘要 |
PURPOSE: A digital delay locked loop having an analog delay member is provided to reduce the layout size, to accelerate locking and to reduce signal jittering noise. CONSTITUTION: The digital delay locked loop includes an input terminal(200), a digital delay, a phase detector(250), a charge pump(260), a voltage controlled delay member(220), a driver(230), and a delay monitor(240). The input terminal inputs a clock signal(CLK) and a clock signal bar(CLKB) to generates an internal clock at either of rising or falling edges. The digital delay receives the output of the input node and adjusts time delay amount. The phase detector receives the internal clock and comparison clock to generate an up signal and down signal. The charge pump receives the up and down signals to generate increased or decreased voltage control signal. The voltage controlled delay member receives the output of the digital delay member and adjusts the time according to the voltage level of the voltage control signal(cvon). The driver generates the internal clock with response to the output of the voltage controlled delay member. The delay monitor receives the output of the driver and generates a comparison clock(comp_clk) having delay same to that of the delayed time.
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