| 摘要 |
PURPOSE: A bit line clamp circuit of a flash memory is provided to improve the reliability and the read speed of a cell by discharging all bit lines to a ground in the time of the change of a standby and an address. CONSTITUTION: In a clamp circuit of redundant cells, NMOS transistors(N1 - N8) are connected to a sense amp(20) by being connected to a global signal line through an NMOS transistor(N9). At this time, the NMOS transistor(N9) is enabled by a sector selection address(SECY<0>). NMOS transistors(N10,N11) are connected between a ground and the global signal line. At this time, the NMOS transistors(N10) is enabled by RCLAMPON, and the NMOS transistors(N11) is enabled by DISCARR. In a clamp circuit of main cells, each NMOS transistor(M0N0 - M0N3) is enabled by a combination of the SECY<0> and an YSA<0:3>. Each NMOS transistor(M0N0 - M0N3) is connected to a global bit line, and the global bit line is connected to an IO sense amp(30) through an NMOS transistor(M0N5). An NMOS transistor(M0N4) is connected between the global bit line and the ground. At this time, the NMOS transistor(M0N4) is enabled by anBLC<0>, and is a clamping transistor.
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