| 摘要 |
PURPOSE: A register delay fixed loop operating in high frequency is provided to materialize a delay fixed loop operating in the high frequency over 200MHz by removing the limitation about the clock cycle time. CONSTITUTION: The register delay fixed loop operating in high frequency includes an input buffer(200), a clock divider(600), a delay model portion(220), a frequency detector(620), a selector(610), a set up time delay portion(630), a phase comparator(230), a phase shift controller(240), a delay monitor(250), a delay fixed loop motor(260) and an output buffer(270). The input buffer(200) inputs the outer clock and buffs it. The clock divider(600) inputs the inner clock signal and generates the pulse appropriate to a clock cycle. The delay model portion(220) receives the feedback signal from the monitor(250) and generates the delay signal, dlic7_r. The frequency detector(620) inputs the output signal of the delay model portion(220), dlic7_r and the output signal of the clock divider(600), dlic4z_r. The selector(610) selects one of two clock cycle pulses. The set up time delay portion(630) compensates the frequency detection error of the frequency detector(620). The phase shift controller(240) controls the shift of delay of the delay monitor(250). The delay monitor(250) controls the output of the phase shift controller(240) and the delay of the input buffer(200). The delay fixed loop motor(260) activates the input buffer(200) and controls the set up time delay portion(630). The output buffer(270) inputs the output of the delay monitor(250) and generates the delay fixed loop clock.
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