| 摘要 |
PURPOSE: A data input device is provided to implement a clock buffer and a data input buffer for doubling an operation speed of a high speed memory without changing circuits of an internal core block. CONSTITUTION: The device comprises a falling clock buffer(12), a double data rate clock controller(11), the first rising clock buffer(13), and the second rising clock buffer(14). The falling clock buffer(12) generates falling clock signals(f_clk) made as pulse signals at falling edges of clock signals in response to a reference voltage signal(vref) and a clock enable signal(clk_en). The double data rate clock controller(11) generates rising clock enable signals whose logic level is inverted at rising edges of the falling clock signals in response to a write level signal(wt_l) and a write pulse signal(wt_p). The first rising clock buffer(13) generates the first rising clock signal in response to rising clock enable signals(rclk_en), the clock signals(clk) and the reference voltage signal(vref). The second rising clock buffer(14) generates the second rising clock signal in response to inverted rising clock enable signals(/rclk_en), the clock signals(clk) and the reference voltage signal(vref).
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