| 摘要 |
PURPOSE: To provide a failure analysis semiconductor device, in which the time required for analyzing a failure can be shortened and a failure detection rate can be also improved. CONSTITUTION: Memory cells, which store data are provided, and a bit line pattern 13A provided with projections and connected to the memory cells is formed. Furthermore, a bit line pattern 13B provided with projections and connected to the memory cells is provided, separating from the bit line pattern 13A by a prescribed space on the same wiring layer with the bit line pattern 13A. In this way, the bit line patterns 13A and 13B are provided, by which the minimum space between the bit line patterns 13A and 13B is elongated in length.
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