发明名称 METHOD FOR METALIZATION OF SEMICONDUCTOR DEVICE
摘要 PURPOSE: A method for forming a metal interconnection line is to provide a self-aligned method, thereby improving insulation characteristics between the interconnection lines, and accurately forming width between the interconnection lines without an effect of a photolithography. CONSTITUTION: A unit device such as a transistor is formed on a silicon substrate. The first insulating layer(1) is formed thereon and then planarized. In consideration of the height of the interconnection line, the lower portion for the interconnection line of the first insulating layer is removed by a predetermined depth, forming a recess. Using the step difference by the recess, an interconnection substance(5) is deposited in desired width of the interconnection line on the entire structure. A sacrificial insulating layer(7) is deposited on the entire structure. A portion between the sacrificial insulating layer and the interconnection substance is etched by an etchant with same selectivity, leaving the interconnection substance only on the sidewall of the sacrificial insulating layer. The interconnection substance in an opposite sidewall of the recess is removed, and the second insulating layer is deposited thereon and then planarized.
申请公布号 KR20010059026(A) 申请公布日期 2001.07.06
申请号 KR19990066404 申请日期 1999.12.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, JIN GUK
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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