发明名称 APPARATUS FOR CONTROLLING ERROR OF PARALLEL BUS SYSTEM
摘要 PURPOSE: An apparatus for controlling an error of a parallel bus system is provided to prevent a system down phenomenon, and to automatically restore a master by temporarily stopping a spurious interrupt error, and by automatically resetting the master. CONSTITUTION: A slave interface unit(100) applies an interrupt request signal(SIRQ*) to a master interface unit(200), and receives an interrupt response signal(SIACK*) from the master interface unit(200). The slave interface unit(100) applies a data transmission response signal(SDTACK*) and a vector number to the master interface unit(200). The master interface unit(200) receives the request signal from the slave interface unit(100), and transmits the signal to an error control unit(300). The master interface unit(200) applies the response signal(EIACK*) to the slave interface unit(100). The error control unit(300) receives the request signal(EIRQ*) from the master interface unit(200), and applies the signal to a CPU(400). The error control unit(300) applies the response signal(IACK*) applied from the CPU(400) to the master interface unit(200). The CPU(400) applies the response signal(IACK*) to the error control unit(300). The CPU(400) applies a clock signal(CLOCK) to the error control unit(300).
申请公布号 KR20010057811(A) 申请公布日期 2001.07.05
申请号 KR19990061221 申请日期 1999.12.23
申请人 LG INFORMATION & COMMUNICATIONS LTD. 发明人 KIM, SANG CHEOL
分类号 G06F11/00;(IPC1-7):G06F11/00 主分类号 G06F11/00
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