| 摘要 |
PURPOSE: An input buffer circuit is provided to be capable of reducing a standby current flowing through a circuit at buffering while maintaining an operation speed of an overall circuit. CONSTITUTION: The first voltage comparator(11) of a cross couple type receives a reference voltage(VREF) for determining a low level and a high level and an input signal(VIN) of a transistor-transistor logic(TTL) level and compares a voltage of the input signal with the reference voltage. The second voltage comparator(12) of a cross couple type operates according to an enable signal(EN) and a logic level of an output signal from the first voltage comparator(11) and compares the voltage of the input signal with the reference voltage. A CMOS inverter(13) receives output voltages of the first and second voltage comparators(11,12) in parallel to output a signal of an inverted voltage level.
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