A method and apparatus for circuit emulation

摘要

An emulation device is provided which has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory (1000) within the emulation device can be configured to emulate blocks of memory on a target processor system. Each block of memory responds to three different memory buses (1012, 1013, 1014) and can receive up the three simultaneous memory request. Arbitration circuitry (1050) selects the highest priority memory request for service on each cycle. Each memory block is configured to respond to a block of addresses beginning at a selected starting address (1031, 1032). Two blocks of memory can be linked (1030b) to form a single merged block of memory in which both arbitration circuits operate in lock step by masking a most significant address bit within an address decoder (1040, 1041, 1042) of the block of addresses selected for the memory block (1035).