| 摘要 |
PURPOSE: A synchronous DRAM capable of being programmable and self refresh is provided to program a self refresh period with desired one by using an address which is not used during mode register setting. CONSTITUTION: The device includes an address buffer(10), an address register(11), a row pre-decoder(13), a mode register(16), a self refresh logic(17), an internal row address counter(20), a bit line precharge control signal generator(21), a memory cell array(22) and a self refresh logic and timer. The self refresh logic and timer uses the signal from the address register which is not used during mode register setting to generate a programmed refresh request signal having plurality of refresh periods. The bit line precharge signal generator is not operated under control of the self refresh logic and timer during self refresh mode. The self refresh logic and timer further includes a decoder which decodes the signal from the address register and a plurality of frequency signal from a frequency divider.
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