PERIPHERAL CIRCUIT LAYOUT METHOD OF SEMICONDUCTOR MEMORY APPARATUS

摘要

PURPOSE: A peripheral circuit layout method of semiconductor memory apparatus is provided to decrease a chip size by layouting a semiconductor apparatus. CONSTITUTION: A block for plural peripheral circuits is elongated in parallel to each other. Each block for the peripheral circuit includes plural logic gates which is composed of at least more than one CMOS transistor. The logic gates becomes layout by a first, second, and third wiring line. An NMOS transistor in a CMOS transistor of the logic gate and a source and a drain of a PMOS transistor are connected to the first wiring lines placed by a metal line on a first direction and a vertical second direction. The NMOS transistor of the specific logic gate among the blocks for the peripheral circuit and the source of the PMOS transistor are common to mutually neighboring the NMOS transistor of the block for the peripheral circuit and the source of the PMOS transistor. The second wiring lines are arranged to the first direction on the logic gate and use an input or output line of the partial gate among the logic gates. An operating electric voltage or a grounding electric voltage power wiring is arranged horizontally to the third wiring line among the blocks for the peripheral circuit and second wiring is connected to the first wiring which is the source of the NMOS transistor on PMOS transistor of the logic gate.