Test circuit for testing a digital semiconductor circuit configuration

摘要

A monolithically integrated test circuit for testing a digital semiconductor circuit configuration that is formed on the same semiconductor chip and has a large number of elements to be tested. The test circuit has a test data pattern register for temporary storage of a test data pattern, a read and write circuit for writing and reading the data in the test data pattern register to and from the elements to be tested, and a comparison circuit. The comparison circuit tests for any difference between the data written to and read from the elements to be tested. The test circuit has a pattern variation circuit, which can be activated by an activation signal and varies the test data pattern from the test data pattern register before writing into the elements to be tested.