发明名称 |
Multi-voltage I/O buffer clamping circuit |
摘要 |
A buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used to interface with multiple voltage levels. The circuit uses a protection transistor in which the gate is controlled by a logic circuit having the mixed voltages as inputs. It is particularly useful on CMOS semiconductor chips that interface with multiple voltage levels which are required to conform to a specification allowing voltage levels to be powered down.
|
申请公布号 |
US6255851(B1) |
申请公布日期 |
2001.07.03 |
申请号 |
US19990366977 |
申请日期 |
1999.08.04 |
申请人 |
AGERE SYSTEMS GUARDIAN CORP. |
发明人 |
STRAUSS MARK S. |
分类号 |
H03K19/003;(IPC1-7):H03K19/018 |
主分类号 |
H03K19/003 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|