Frequency acquisition circuit and method for a phase locked loop

摘要

A circuit (14) for aiding proper frequency lock in a phase locked loop (12) includes a phase detector (40) adapted for receiving an input signal and an oscillator output signal from the phase locked loop (12) and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal. An up cycle slip detector (42a) receives the up pulse width modulated cycle slip signal and generates an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal. A down cycle slip detector (42b) receives the down pulse width modulated cycle slip signal and generates a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal. A phase correction circuit (41, 43) is provided for generating a steering signal in response to the up and down cycle slip signals.