发明名称 |
Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines |
摘要 |
A memory 1300 including an array of rows and columns of memory cells 501 is disclosed. For each column, first and second interdigitated bitlines 1301, 1303 are coupled to the cells of the column. The first bitlines 1301 has an end coupled to a sense amplifier 1302 at a first boundary of the array and a second bitline 1303 has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry 508 precharges the first bitlines 1301 of the columns of the array substantially simultaneous to an access to the array through the second bitlines 1303 of selected columns of the array.
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申请公布号 |
US6256221(B1) |
申请公布日期 |
2001.07.03 |
申请号 |
US20000507106 |
申请日期 |
2000.02.17 |
申请人 |
SILICON AQUARIUS, INC. |
发明人 |
HOLLAND WAYLAND BART;WALLER CRAIG;RAO G. R. MOHAN |
分类号 |
G11C7/18;G11C8/12;G11C8/16;G11C11/405;G11C11/406;G11C11/4097;(IPC1-7):G11C11/24 |
主分类号 |
G11C7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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