| 摘要 |
PURPOSE: A method for controlling a bus is provided to enhance system efficiency by preventing a data transmitting speed from being decreased on a bus line. CONSTITUTION: A serial clock control unit(2) and a data control unit(4) transmit/receive a SCL and a SD being exchanged thereto on a bus. A serial clock free scalar(5) decides a SCL frequency. The elements included in the internal register unit(10) are described as follows. A free scalar register(11) stores a SCL frequency. An interrupt register(12) indicates a receiving completion, a transmitting completion, a FIFO empty, a FIFO full, and a response. A control register(13) controls a transmitting mode, a receiving mode, a response enable, a data transmitting start, a stop, a busy, a consecutiveness, and a reset. A FIFO control register(16) controls a FIFO empty, a full, a flush etc. A FIFO transmitting/receiving register(17) stores an address to be transmitted. In addition, the internal register unit(10) includes a counter register(14), a buffer register(15) and a FIFO register(18). A shift buffer register(6) shifts data(3:0) being transmitted/received through the bus and transmits or receives the data to a SCL. A FIFO register(18) consists of 32-bit.
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