发明名称 DEMULTIPLEXER CIRCUIT WITH BYTE SYNCHRONIZATION FUNCTION
摘要 PROBLEM TO BE SOLVED: To solve problems of a conventional demultiplexer circuit with a byte synchronization function that has required a complicated design, had a limit in a pattern size and an insufficient timing margin and to provide a general-purpose circuit acted in a stable operation because the conventional circuit has been limited to a shift register type, cannot have utilized a design resource of a conventional demultiplexer due to the common use of the shift register with a pattern detection circuit and has required an exclusive design. SOLUTION: A byte parallel processing section for an SDH frame signal is configured separately from a pattern detection section for detecting a byte border. Thus, either of a tree type demultiplexer and a shift register type demultiplexer can be available for a circuit executing byte parallel processing. Furthermore, since the pattern detecting section adopts a shift register of a separate configuration, number of bits of a fixed pattern can freely be set.
申请公布号 JP2001177490(A) 申请公布日期 2001.06.29
申请号 JP19990361173 申请日期 1999.12.20
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KAWAI KENJI;ICHINO HARUHIKO
分类号 H03M9/00;H04J3/00;H04J3/06;H04L7/08 主分类号 H03M9/00
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