| 摘要 |
<p>A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion. The method includes identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals representing an unknown state in response to conditions under which the first defective portion is likely to malfunction.</p> |
